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TechnologyPublished: 8 September 2026 at 14:09

Samsung and TSMC commit to ASML's next-generation chipmaking tools

Samsung and TSMC are joining Intel in adopting ASML's new High NA EUV lithography machines, aiming to ease chip production bottlenecks. The three firms also launched an initiative to shift to larger 12-inch photomasks.

Foto: Engadget

Dutch equipment maker ASML has announced that Samsung and TSMC, the world's two largest chip manufacturers, will follow Intel in adopting its latest High NA extreme ultraviolet (EUV) lithography machines for chip fabrication.

According to ASML, Samsung intends to use the technology for DRAM memory production by 2028, while TSMC plans to deploy it in advanced production nodes starting in 2030. So far, High NA EUV has only been used commercially by Intel, which applies it in its 18A process for select Core Ultra Series 3 (Panther Lake) processors — the company has already produced more than a million wafers using the technology. Intel is also developing an enhanced version called 18A-P, which Apple is reportedly considering for future A-series iPhone chips.

Larger photomasks

ASML has also launched a joint initiative with TSMC and Samsung to move from the current six-inch photomask standard to larger 12-inch masks, which are used to stencil chip patterns onto wafers. TSMC said the larger masks would boost fab productivity, cut manufacturing costs, and eliminate the need for "stitching" — a costlier process currently required to combine smaller chip features into larger designs.

Testing of 12-inch photomask facilities is set to begin in 2031, with production expected to start in 2033. Another major chipmaker, SK Hynix, is reportedly evaluating whether to join the initiative.

ASML chief technology officer Marco Pieters told Reuters that if the industry successfully makes the transition, equipment productivity could rise by roughly 40 percent. However, as Intel's experience has shown, adopting the new technology is not straightforward, and both Samsung and TSMC could face obstacles that delay their target timelines.

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